1. Field of the Invention
The present invention generally relates to testing of semiconductor integrated circuits during manufacture and, more particularly, to the testing of combinatorial logic arrays using level sensitive scan testing techniques.
2. Description of the Prior Art
Increased integration density has greatly increased the functionality, performance and economy of manufacture of integrated circuit devices due to the increased number of active elements which may be placed in greater proximity on chips simultaneously formed on a wafer. However, freedom from manufacturing defects must be ascertained by propagating a sufficient number of different combinations of logic level signals therethrough to be able to determine that the device will perform correctly for any digital signals applied thereto.
For relatively simple circuits that involve relatively few inputs and relatively few dependencies on prior execution cycles, a relatively small and simple test program may be constructed to ascertain freedom from manufacturing defects. However, with the increased functionality of integrated circuit device and the corresponding increase in number of inputs and dependencies on numerous prior execution cycles, it is unacceptably time-consuming and complex to create test programs to pre-condition inputs to the correct state for testing even only one combination of inputs. The corresponding test time is also prohibitive.
To reduce testing time and simplify the test generation process, a design referred to as level sensitive scan design (LSSD) is employed. The current practice of implementing LSSD is to provide a separate test input port to all registers in the device and to connect the output of each register to the test port of another register to form scan chains throughout a sufficient portion of the device to provide inputs to and collect outputs from logic arrays to be tested. Several parallel scan chains can be formed in this manner if desired. In this way, signals to be applied to the logic array can be loaded into the registers by scanning and the registers used to provide signals in parallel to the logic array(s) via the test path. The output of the logic arrays could be collected in a similar register using a mode switch or other expedient for each register stage. Using this technique, additional gains in testing time reduction were sought by providing direct control of logic inputs via the register(s), partitioning the logic arrays into blocks and testing a plurality of partitions concurrently in parallel.
However, to reduce the LSSD test structure, design costs and possibly chip area occupied by the test path and associated controlling logic (which are not used during normal operation of the chip), input and ouput circuits of portions of the test path are not generally optimized to operate at the high normal speed cycle time of the chip. Therefore, substantial time was required for loading and unloading the test register. In theory, this loading and unloading time could be reduced by configuring the register in a plurality of segments to obtain a number of stages equal to the number of inputs to logic array partitions to be simultaneously tested. However, the number of input and output pins provided on test apparatus is limited and cost of test apparatus increases dramatically with the number of input and output pins provided since the tester apparatus must be substantially replicated for each input/output pair of pins. The number of parallel sections of the test register that can be provided is thus limited, as a practical matter, to the number of input or output pins provided in the tester apparatus.
Therefore there is a trade-off between the number of parallel sections of the test register on the chip (which can be loaded and unloaded at a lower rate or longer cycle time) and the cost of the test apparatus. Since the cost of tester overhead during a test is the primary reason for seeking to reduce level sensitive scan test time, there is little gain to be obtained by reduction of loading and unloading time by using plural parallel test register sections which can only be accommodated by a more expensive tester apparatus. Similarly, reduction of the length of test register sections to reduce loading and unloading time of the test register sections by limiting the number of logic array partitions (and/or the size thereof) provides little if any reduction in cost of tester overhead when the number of tests must be correspondingly multiplied to test a given number of logic array gates.
In other words, if the loading and unloading time is halved by using two parallel test register sections but the provision of a second pair of input and output pins to accommodate the two test register section doubles the cost of the tester apparatus, there would be no reduction in the cost of tester overhead. Similarly, if the loading and unloading time is halved by reducing the number of signals to be provided to a reduced number or size of logic array partitions simultaneously tested but the number of tests per chip were correspondingly doubled, there would be no reduction (and probably an increase) in the cost of tester apparatus overhead. Accordingly, reduction of the length of test register sections for a given number of signals to be applied to and collected from logic array partitions is limited by the capacity of the tester apparatus (and, in turn, limits the number of logic array partitions which can be simultaneously tested) and the loading and unloading time of the test register dominates the cost of level sensitive scan testing.
It should also be recognized from the foregoing that the configuration of the test register establishes a minimum number of input/output pin pairs required for a tester apparatus adequate to perform level sensitive scan testing of chips including a test register of a given design. While it is possible to reconfigure a test register, provision of such a facility would require additional expenditure of design time in regard to the test register which is non-functional during normal operations. By the same token, optimization of the test register input/output circuits to increase signal propagation speed therethrough increases chip cost without producing any functional benefit during normal operation of the chip. In general, given the capacity of test registers required to significantly reduce testing time, the cost of increasing signal propagation speed thereof (including additional design time and resources to optimize the LSSD test structure for speed and the possible increase of chip area to do so) cannot be fully compensated by reduction of cost of tester apparatus overhead. Therefore, at the present state of the art, no technique or apparatus is available that can significantly reduce the time and/or cost of level sensitive scan testing of integrated circuit chips.
It is therefore an object of the present invention to provide a test register which can be rapidly loaded and unloaded at high speed comparable to or even substantially exceeding normal high clock cycle speed of the integrated circuit and is of arbitrary size and configuration, independent of tester apparatus input/output pin capacity.
It is another object of the invention to provide a technique and apparatus for reducing time and tester apparatus overhead for level sensitive scan design testing of integrated circuits.
It is a further object of the invention to provide a technique and apparatus for performing level sensitive scan design testing with apparatus providing an arbitrarily small number of input/output pin pairs.
It is yet another object of the invention to provide for reduction of LSSD testing time without optimization or redesign for shift rate increase of test registers or scan chains.
In order to accomplish these and other objects of the invention, an integrated circuit is provided having a logic array and configurable registers forming scan chains with respective stages connected to inputs and outputs of the logic array, comprising a source shift register including a number of stages equal to a number of scan chains and having each stage connected to an input of a respective scan chain, a sink shift register including a number of stages equal to a number of scan chains and having each stage connected to an output of a respective scan chain, and scan chain input and output circuits clocked at a test clock rate less than a normal high speed clock rate of the chip.
In accordance with another aspect of the invention, a method of performing level sensitive scan design testing of an integrated circuit chip comprising steps of configuring registers on the chip into scan chains having respective register stages connected to respective inputs and outputs of a legic array to be tested, shifting data through the scan chains at a test clock rate lower than a normal clock rate of the chip, providing test data to the scan chains through a source shift register clocked at a high speed clock rate, and collecting outputs from the scan chains through a sink shift register clocked at a high speed clock rate; the high speed clock rate being higher than the clock rate applied to the scan chains and comparable to or exceeding the normal high speed clock rate of the chip.